发明名称 |
Issuing instructions out of order in data processing |
摘要 |
To implement an early data dependency resolution mechanism for a high-performance data processing system that utilises out-of-order instruction issue, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines each capable of storing multiple instructions 50. The register-dependency cache contains an identical number of cache lines each capable of storing an identical number of register-dependency units 52 as there are instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units 52 are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified and translated to its respective instruction utilising a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle. Since each register-dependency unit 52 has fewer bits than an instruction 50, more of them can be fetched per processor cycle. |
申请公布号 |
GB2320775(A) |
申请公布日期 |
1998.07.01 |
申请号 |
GB19970021623 |
申请日期 |
1997.10.14 |
申请人 |
* INTERNATIONAL BUSINESS MACHINES CORPORATION;* MOTOROLA INC |
发明人 |
MUHAMMAD N * AFSAR;ROMESH M * JESSANI;SOUMMYA * MALLICK;ROBERT G * MCDONALD;MUKESH * SHARMA |
分类号 |
G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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