| 摘要 |
<p>Disclosed is a refresh address test circuit of a semiconductor memory device having a self-refresh function using a plurality of internal refresh address signals, comprising a plurality of the address test paths, each including a first sub-path with an initial logic level of the refresh address signal and a second sub-path of refresh address signal, a plurality of comparators, each receiving the initial logic level of the refresh address signal from the first sub-path and a present logic level of the refresh address signal from the second sub-path, a test output circuit for receiving the output signals generated from the plurality of comparators. <IMAGE></p> |
