发明名称 |
Memory system including an on-chip temperature sensor for regulating the refresh rate of a dram array |
摘要 |
<p>A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures. By controlling the refresh rate dependent upon the temperature of the semiconductor die, proper state retention is ensured within each of the memory cells while allowing performance to be optimized. <IMAGE></p> |
申请公布号 |
EP0851427(A2) |
申请公布日期 |
1998.07.01 |
申请号 |
EP19970122271 |
申请日期 |
1997.12.17 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
IRRINKI, SWAMY V.;KAPOOR, ASHOK;LEUNG, RAYMOND;OWENS, ALEX;WIK, THOMAS R. |
分类号 |
G11C11/406;G11C11/56;(IPC1-7):G11C11/406 |
主分类号 |
G11C11/406 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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