发明名称 DEVICE AND METHOD FOR DEBUGGING LOGIC CIRCUIT MODEL
摘要 PROBLEM TO BE SOLVED: To provide a debugging device which can easily restore the state immediately before a logic circuit model causes a trouble without setting any check point, etc. SOLUTION: A simulator management device 11 monitors whether or not the value of an object to be observed in a logic circuit model 14 simulated by a logic simulator 12 (a) coincides with an expected value stored in an expected value file 15 by controlling the execution of two logic simulators 12 (a) and 12 (b) in parallel so that the operations of one simulator 12 (b) can be delayed by one action from that of the other simulator 12 (a). When uncoincidence occurs, the device 11 stops the operations of the simulators 12 (a) and 12 (b) so as to make the simulator 12 (b) maintain the state immediately before the logic circuit model 14 causes a trouble.
申请公布号 JPH10177590(A) 申请公布日期 1998.06.30
申请号 JP19960338546 申请日期 1996.12.18
申请人 TOSHIBA CORP;TOSHIBA COMPUT ENG CORP 发明人 SUZUKI MASAKI;SHIBATA YUKIHIKO;UENO YUTAKA;TAKEDA HIROYUKI;KINOSHITA KOJI
分类号 G01R31/28;G06F17/00;G06F17/50;G06F19/00;G06Q50/00;G06Q50/04;H01L21/82 主分类号 G01R31/28
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