发明名称 |
METHOD AND APPARATUS FOR TESTING MULTI-PORT MEMORY |
摘要 |
A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wired short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs and exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address. |
申请公布号 |
CA2219844(A1) |
申请公布日期 |
1998.06.30 |
申请号 |
CA19972219844 |
申请日期 |
1997.10.31 |
申请人 |
LOGICVISION, INC. |
发明人 |
NADEAU-DOSTIE, BENOIT;C TE, JEAN-FRANCOIS |
分类号 |
G11C8/16;G11C29/28;(IPC1-7):G11C29/00 |
主分类号 |
G11C8/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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