| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory cell array comprising, while occupying a surface area which is suppressed to a minimum, a layout of capacitor under a bit-line (CUB) structure. SOLUTION: In a memory cell layout 10, a plural number of capacitors 12 are formed on a semiconductor substrate, in a pre-determined array 10 comprising respective row 14 and columns 16. At least one bit-line 18 interacts with the plural capacitors 12 for electric signal. At lest one bit-line contact is formed, together with at least one bit-line 18. At least one bit-line contact is assigned in a region 32 positioned at an intermediate point among four capacitors 12 among a plural number, so as to interact with one selected from among the four of a plural number of capacitors for electric signal. Thus, a minimum surface area for the combination of at least one bit-line 18 and four plural number of capacitors is occupied. |
