INTEGRATED PROCESSOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To eliminate the barrier problems of a memory, i.e., the large electric power and a chip area are needed to eliminate a velocity gap between a CPU and the memory by preparing a main memory, a CPU and a full-width cache. SOLUTION: An on-chip memory system 103 includes a CPU 102, 16 pieces of memory blocks 104 and a victim cache 106. Every block 104 includes a main memory bank 118, an instruction cache bank 120 and a data cache bank 122 which are corresponding to each other. A CPU 102 produces an address in an address space of the bank 118. If a cache bank miss occurs, a cache bank logic replaces the victim cache line of a cache line with a new one including the corresponding row of the corresponding memory bank that is designated by a sent address.