发明名称 Central processing unit detecting and judging whether operation result executed by ALU in response to a first instruction code meets a predetermined condition
摘要 A central processing unit in a microprocessor, or the like, executes at high speed a simple program and sets a different immediate depending on a true or false state of a predetermined condition. In the central processing unit, the first and second immediates are set in the instruction code, which is prefetched by an instruction queue. Depending on whether a value of one or zero is stored in the zeroflag, which corresponds to the true or false state of the predetermined condition, the first or second immediate is written into an address location of the register or the memory designated by the same instruction code.
申请公布号 US5774687(A) 申请公布日期 1998.06.30
申请号 US19950483064 申请日期 1995.06.07
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 NAKAMURA, KAZUO;MATSUI, HIDEO
分类号 G06F9/305;G06F9/30;G06F9/302;G06F9/318;G06F9/32;G06F9/38;(IPC1-7):G06F9/00 主分类号 G06F9/305
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