发明名称 METAL WIRING STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
摘要 PROBLEM TO BE SOLVED: To enable the simultaneous solution of problems, which are generated in a cell array region and a peripheral circuit region during the process of a metal wiring, by a method wherein a material layer for the lower electrode of a ferroelectric capacitor is applied as a local interconnection wiring which discharges the role of the metal wiring. SOLUTION: As a local interconnection wiring, that is, a first metal wiring 109b is obtained by patterning a first metal layer, which consists of a platinum element, for a lower electrode of a ferroelectric capacitor, the contact resistance between the metal wiring 109b and the first metal layer is not increased even if a Ti layer, which is an ohmic layer, is not used unlike a conventional metal wiring method using an aluminium wiring. Moreover, second interlayer insulating layers 115 are formed on the upper parts of resultant materials in a cell array region and a peripheral circuit region. At this time, for coupling second metal wirings 119 with each other, via holes are formed in the upper part of the capacitor in the cell array region and via holes are formed in the upper part of the wiring 109b in the peripheral circuit region.
申请公布号 JPH10178157(A) 申请公布日期 1998.06.30
申请号 JP19970301633 申请日期 1997.11.04
申请人 SAMSUNG ELECTRON CO LTD 发明人 BOKU JINZEN;KIN HEIKI;GO SEISHUN;RI SOBIN
分类号 H01L21/8247;H01L21/28;H01L21/8239;H01L21/8242;H01L21/8246;H01L27/10;H01L27/105;H01L27/108;H01L29/788;H01L29/792 主分类号 H01L21/8247
代理机构 代理人
主权项
地址