发明名称 |
Reduced gate error detection and correction circuit |
摘要 |
Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit position. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.
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申请公布号 |
US5774481(A) |
申请公布日期 |
1998.06.30 |
申请号 |
US19950414064 |
申请日期 |
1995.03.31 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MEANEY, PATRICK JAMES;CHEN, CHIN-LONG |
分类号 |
G06F11/10;H03M13/13;(IPC1-7):H03M13/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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地址 |
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