| 摘要 |
PROBLEM TO BE SOLVED: To obtain a memory having effect that almost complete software error can be corrected during access operation without access delay by providing a DRAM having an error correction circuit only during refreshing other than access operation. SOLUTION: Read-out of data bits stored in a memory cell array 102 conforms to read-out of a standard DRAM. Writing in the memory cell array 102 comprises decoding of a standard column address, latch of a sense amplifier, decoding of a column address, connecting an input/output bus to a sense amplifier of a column in which an address is specified so as to latch a new bit, separating a bit line, and non-activation of a column. Writing sets additionally '1' to an ECC abolition memory cell of a row, and it is displayed that writing is performed in this row. |
