| 摘要 |
PROBLEM TO BE SOLVED: To provide a method of forming a silicide layer with a small sheet resistance on an electrode in a MOS device. SOLUTION: This structure 40 for integrated circuit is formed, at the time MOS transistors are produced. It is covered with a silicide layer 56, having various parts with different thicknesses. Namely, it is provided with a substrate 42, a source 44/drain 46 electrode thereon, a gate containing a gate-insulating sidewall 54 containing a gate-insulating layer 50 provided on the upper side of a channel area 48, a gate electrode 52 provided on the gate insulating layer 50 and a gate-insulating sidewall 54, surrounding the gate electrode 52 entirely, and a metallic silicide layer 56 on the source 44/drain 46 electrode, a gate electrode 52 and a gate sidewall 54. The metallic silicide layer 56 contains a part having a first thickness on the source 44/drain 46 electrode and the gate electrode 52 and a part having a second thickness smaller than the first thickness on the gate sidewall 54. |
