发明名称 A method and a circuit for generating a system clock signal
摘要 A method of generating a system clock signal by means of a controlled oscillator (2), wherein the system clock signal may periodically be locked to a selected one of a plurality of external reference signals, comprises measuring a phase difference between the reference signal and the system clock signal for each of the external reference signals, and using the measured phase difference for the selected reference signal to control the controlled oscillator. A corresponding circuit for generating a system clock signal includes means (11, 12; 17) for each of the external reference signals for measuring a phase difference between the reference signal and the system clock signal and for generating an error signal in response to the measured phase difference. The circuit comprises means (13) for selecting one of the measured error signals and for using this to control the controlled oscillator (2).
申请公布号 AU5117298(A) 申请公布日期 1998.06.29
申请号 AU19980051172 申请日期 1997.12.02
申请人 DSC COMMUNICATIONS A/S 发明人 OLE RASSING ANDERSEN
分类号 H04J3/06;H04L7/033 主分类号 H04J3/06
代理机构 代理人
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