| 摘要 |
PROBLEM TO BE SOLVED: To effectively use the hardware resources and to reduce the circuit scale by preparing an arithmetic unit which performs the 1st IDCT(inverse discrete cosine transform) by means of a multiplier and an adder and then performs the 2nd IDCT via the cumulative shift addition of partial products. SOLUTION: When the one-dimensional IDCT processing is performed, the one-dimensional coupling that is secured by performing the multiplication via a multiplier 102 and the cumulative addition via an adder 106, is required for an operation. For this purpose, a selection means 105 selects the input with the number of bits equivalent to the accuracy needed for the 1st one-dimensional IDCT processing among the external inputs. At the same time, a selection means 104 selects the data inputted from the means 107. When the 2nd one- dimensional IDCT processing is performed, the means 107 and 104 select the output of the adder 106 and the external input respectively. Then the cumulative shift addition of partial products is performed via the shift of higher and lower order bits that is carried out by a shifter 103. |
