| 摘要 |
PROBLEM TO BE SOLVED: To reduce the jitter of an oscillating signal obtained by a PLL circuit without adding a large modification to the circuit configuration of a voltage control oscillator(VCO) for generating the oscillating signal. SOLUTION: In the case where an oscillating signal having the same frequency as a reference signal Sref is generated by the PLL circuit composed of a phase comparator 10, a loop filter 20, a VCO 30a and a divider 40, an oscillating signal S30 is divided by the divider 40 and acquiring the oscillating signal S40 which has a target frequency. Thus, the jitter of the obtained oscillating signal S40 is reduced comparing with the case where it is directly generated by a VCO having a target frequency, and the reducing of jitter is realized without adding large modification to the configuration of VCO. |
