发明名称 TEST FACILITATION CIRCUIT FOR MICROPROCESSOR
摘要 PROBLEM TO BE SOLVED: To easily test a microprocessor containing a cache memory at the low cost by building in the internal circuits excluding an internal circuit that executes a text program stored previously in the cache memory and performs the input/output operations to the outside. SOLUTION: In a normal operation mode, a specific address that does not exist in a cache memory 1 and requires no conversion is outputted from a sequence control unit 6 when a reset state is canceled. When a test mode is set at a mode register 11, an address (test reset address) that accesses a cache instruction is selected. Then an instruction group (test program) which is previously written in the memory 1 in a cache test mode is executed. The test result is rewritten in a data cache by a store instruction, etc. The contents of the memory 1 are read out in a cache test mode and compared with the expected value by a tester for the decision of the acceptance or rejection of the contents.
申请公布号 JPH10171676(A) 申请公布日期 1998.06.26
申请号 JP19960329892 申请日期 1996.12.10
申请人 TOSHIBA CORP 发明人 MORI JUNJI
分类号 G06F11/22;G06F11/267;G06F12/08;G06F15/78 主分类号 G06F11/22
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