发明名称 SIGNAL INTERPOLATION AND DECIMATION USING FILTER SYMMETRY
摘要 PROBLEM TO BE SOLVED: To reduce the complicated multiplication and addition in an interpolating mechanism or a decimation mechanism and to improve the signal efficiency for interpolation and decimation by finding the symmetry of weight applied to one sample and using it. SOLUTION: An adding mechanism 308A receives a source sample X(N) from a terminal 302, receives a source sample X(N-5) from a delay unit 304E, and generates a signal indicating the sum of the source sample X(N) and the source sample X(N-5). A multiplying mechanism 310A receives the signal indicating the sum of the source samples X(N) and X(N-5) from the adding mechanism 308A, and generates a signal indicating the arithmetic product of the sum and the value of composite weight c00. The composite weight c00 is taken out from a memory or a processor. The signal generated by the adding mechanism 308A is used two times. The number of adding mechanisms necessitated for generating interpolation samples Y0-Y3 is made smaller than the number of adding mechanisms necessitated for generating interpolation signals by using a conventional technique.
申请公布号 JPH10173483(A) 申请公布日期 1998.06.26
申请号 JP19970211419 申请日期 1997.06.30
申请人 SUN MICROSYST INC 发明人 MOU ALEX ZHI-JIAN
分类号 H04N5/14;G06F17/10;G06F17/17;G10L19/00;H03H17/00;(IPC1-7):H03H17/00;G10L9/00 主分类号 H04N5/14
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