发明名称 MEMORY ARCHITECTURE FOR A MULTIPLE FORMAT VIDEO SIGNAL PROCESSOR
摘要 <p>A video decoder (10) transcodes video data from various input formats to a predetermined output format. Input data may be standard definition (NTSC or PAL) data or MPEG2 compressed data. Standard definition data are rearranged into block format to be compatible with the decoder's (10) single display processor (40). The display processor selectively processes and conveys either MPEG2 format data or non-MPEG2 format data to a display device. A block based frame memory (20) stores MPEG2 and non-MPEG2 pixel block data, as well as standard definition data in raster line format during processing.</p>
申请公布号 WO1998027721(A1) 申请公布日期 1998.06.25
申请号 US1997022854 申请日期 1997.12.15
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