| 摘要 |
The invention relates to demultiplexing of high frequency data signals. The data signal is first frequency divided before extracting a clock signal, which is necessary to sample the data signal to provide plural, parallel data channels. The data signal is divided into two sub-signals (D1, D2) by means of toggle circuits (1, 2). On the basis of the sub-signal (D2), the circuit (3) generates a clock signal (CP1), which is used for sampling the sub-signals precisely at the time which causes transfer of information in the data signal to the respective channel. The output signal is generated via the XOR circuit (6), which recombines the sampled sub-signals, and finally the output signal is adjusted by means of the XNOR circuit (8) in accordance with the initial state of the sub-signals (D1, D2).
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