发明名称 Verfahren zum Bilden von Metall-Leitungen einer Halbleitervorrichtung
摘要 A barrier layer 12 (eg TiN) is formed over an interlayer insulator layer 11, an interconnect layer 13 (eg tungsten) is formed over the barrier layer, and an antireflection film 14 is formed over the interconnect layer. A patterned photoresist layer 15 is used for masking the underlying metallic layers during a high density plasma etch at low temperature. A highly selective etch process which produces vertical sidewalls is obtained by increasing the source power and decreasing the bias power, and by adjusting the element concentration ratio in the etch gas.
申请公布号 DE19756227(A1) 申请公布日期 1998.06.25
申请号 DE19971056227 申请日期 1997.12.17
申请人 HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., ICHON, KYOUNGKI, KR 发明人 LEE, SEOUNG WOOK, ICHON, KYOUNGKI, KR;SEOL, YEO SONG, ICHON, KYOUNGKI, KR;CHOI, CHANG JU, ICHON, KYOUNGKI, KR
分类号 H01L23/52;H01L21/302;H01L21/3065;H01L21/3205;H01L21/768;(IPC1-7):H01L21/768;C23F1/12 主分类号 H01L23/52
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