Circuit for modulo-address generation with reduced circuit area

摘要

The circuit has an adder (21) which adds received current address and an address increment values. An adder subtractor (22) either adds or subtracts a data range parameter to or from the incremented address value according to the sign of the data range value to produce a revised address value. An output selection circuit (30) selects the incremented address value for the next address value if the sign bit is positive and the revised value is less than a minimal address value for the data range or if the sign bit is negative and the incremented value is greater than or equal to the minimal value. The revised value is selected if the sign bit is positive and the revised value is greater than or equal to the minimal value or if the sign bit is negative and the incremented value is less then the minimal value.