发明名称 METHOD AND SYSTEM FOR INCREASED SYSTEM MEMORY CONCURRENCY IN A MULTIPROCESSOR COMPUTER SYSTEM
摘要 A method and system are disclosed for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible 5 in associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and this change bit is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate including accessible fields the reference bit and change bit may be concurrently updated by multiple processors, increasing memory concurrency.
申请公布号 CA2107056(C) 申请公布日期 1998.06.23
申请号 CA19932107056 申请日期 1993.09.27
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 OEHLER, RICHARD RAPHAEL;KAHLE, JAMES ALLAN;MUHICH, JOHN STEPHEN;SILHA, EDWARD JOHN
分类号 G06F15/16;G06F12/10;G06F15/177;(IPC1-7):G06F15/16 主分类号 G06F15/16
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