| 摘要 |
In a conventional random test generator, instructions are generated, pushed onto a queue, and then popped off of the queue in generation order. The methods and apparatus disclosed herein provide a means of associating a delay with each generated instruction. Instructions are therefore popped off of the queue in response to their associated delay, rather than in generation order. Since the delay associated with each instruction of a synthesizing sequence (e.g., a load sequence) is randomly generated, a synthesizing sequence may be generated numerous times, yet never appear as the same sequence of instructions to a device under test. Furthermore, no register is reserved for a special purpose. As a result, the disadvantages of conventional instruction generating techniques are overcome. |
