发明名称 |
High speed system for grey level image scaling, threshold matrix alignment and tiling, and creation of a binary half-tone image |
摘要 |
A system converts a source image of grey level pixel values into a destination image of binary pixel values, the source and destination images having different levels of resolution. The system includes a memory which stores at least a portion of a row of source pixels, a corresponding row of a grey level threshold matrix and a relative input index array (RIIA) which employs a single index bit for each column of the destination image. Index bits are read from the memory and placed in an index bit register, and N source pixel values are written into a source register. A scale logic circuit includes N destination image column outputs and is responsive to each index bit, to output one grey level source pixel on each output. An alignment switch is responsive to a clock input to provide N threshold pixel value outputs that are aligned with corresponding destination image pixels. A comparator compares each source grey level pixel with a corresponding threshold pixel value and assigns a binary value in accordance with the comparison action. A controller initially loads the registers with values from the memory and then synchronously operates the system to output, in parallel, N destination image binary pixel values per clock cycle.
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申请公布号 |
US5771105(A) |
申请公布日期 |
1998.06.23 |
申请号 |
US19960606468 |
申请日期 |
1996.03.04 |
申请人 |
HEWLETT-PACKARD COMPANY |
发明人 |
RUST, ROBERT A.;FUJII, DAVID B. |
分类号 |
H04N1/387;G06T3/40;G06T5/00;H04N1/40;H04N1/405;(IPC1-7):G06K9/36 |
主分类号 |
H04N1/387 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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