发明名称 |
ATM cell synchronous system |
摘要 |
An asynchronous transfer mode (ATM) cell synchronizing method and circuit used in a digital network system in which: an 8 bit ATM cell stream of a received signal is inputted into a five-stage D flip-flop and outputted to a first adder (exclusive OR) circuit through a remainder operation circuit; the adder circuit evaluates exclusive OR of the output of the remainder operation circuit and the inputted 8 bit ATM cell stream, the result of such an evaluation is inputted into a one-stage D flip-flop through a second adder; and the output of this one-stage D flip-flop is inputted into a CRC arithmetic operation circuit having a generating polyominal X8+X2+) X+1 and also into a decoder. The output of the CRC arithmetic operation circuit is inputted back to the second adder, and a cell synchronizing pulse is outputted from the decoder.
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申请公布号 |
US5771249(A) |
申请公布日期 |
1998.06.23 |
申请号 |
US19950523191 |
申请日期 |
1995.09.05 |
申请人 |
TOYO COMMUNICATION EQUIPMENT CO., LTD. |
发明人 |
YANAGISAWA, SHIGEKI |
分类号 |
H04L7/04;H04L12/56;H04Q11/04;(IPC1-7):H03M13/00;H04L7/00 |
主分类号 |
H04L7/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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