发明名称 |
MULTIPLE INSTRUCTION SET MAPPING |
摘要 |
<p>A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core 2 via an instruction pipeline 6. As program instruction words of a second instruction set pass along the instruction pipeline, they are mapped to program instruction words of the first instruction set. The second instruction set has program instruction words of a smaller bit size than those of the first instruction set and is a subset of the first instruction set. Smaller bit size improves code density, whilst the nature of the second instruction set as a subset of the first instruction set enables a one-to-one mapping to be efficiently performed and so avoid the need for a dedicated instruction decoder for the second instruction set.</p> |
申请公布号 |
EP0758463(B1) |
申请公布日期 |
1998.06.17 |
申请号 |
EP19950908326 |
申请日期 |
1995.02.15 |
申请人 |
ADVANCED RISC MACHINES LTD. |
发明人 |
JAGGAR, DAVID VIVIAN |
分类号 |
G06F9/38;G06F9/30;G06F9/318;(IPC1-7):G06F9/318 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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