Universal input data sampling circuit

摘要

A circuit for selecting a clock edge for data input sampling is described. An input data signal is sampled at a rising edge of an input clock to generate a first interim data signal and an error-rise signal is asserted if designated set-up time and hold time requirements are not met. Similarly, the input data signal is sampled at a falling edge of the input clock to generate a second interim data signal and an error-fall signal is asserted if designated set-up time and hold time requirements are not met. The first interim data signal is output if the error-fall signal is asserted and the second interim data signal is output if the error-rise signal is asserted.