发明名称 |
Clock signal supplying circuit |
摘要 |
A clock signal generated by a clock signal generating circuit is supplied to a frequency-dividing circuit formed using a D-type flip-flop circuit, being supplied to a controlled circuit after being divided down. Furthermore, the clock signal generated by the clock signal generating circuit is supplied to the controlled circuit by way of a through circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity of the frequency-dividing circuit, the through circuit being formed using the D-type flip-flop circuit in the same way as the frequency-dividing circuit.
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申请公布号 |
US5767720(A) |
申请公布日期 |
1998.06.16 |
申请号 |
US19960686041 |
申请日期 |
1996.07.25 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
OSERA, SHINICHI;SAEKI, YUKIHIRO |
分类号 |
H03K5/00;H03K5/15;H03K21/08;(IPC1-7):H03K5/13 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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