| 摘要 |
Integrated circuits having single and multiple device modes are described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a "by n" input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a "xn" configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a "x2n" configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.
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