Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts,申请号US08/450765-传众专利搜索

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发明名称	Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts
摘要
申请公布号	USRE35825(E1)	申请公布日期	1998.06.16
申请号	US08/450765	申请日期	1995.05.24
申请人		发明人
分类号		主分类号
代理机构		代理人
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