发明名称 |
Bus interface logic system |
摘要 |
A system and method of synchronizing data transfers between two processors having different bus transactions by providing a buffer for storing the data and a control logic for dividing a concurrent address and data bus transactions into an address bus transaction followed by a data bus transaction. During a read operation, the requesting device is forced to wait for data availability before entering the data bus transaction. During a write operation, the data bus transaction is delayed by using a storage mechanism that effectively separates the address transaction from the data transaction. The present invention also provides direct memory access fly-by operations between an input/output device and a memory device. These operations are accomplished by isolating a secondary bus from the system bus and allowing the destination device to capture the requested data as soon as it is available on the system bus.
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申请公布号 |
US5768550(A) |
申请公布日期 |
1998.06.16 |
申请号 |
US19950560758 |
申请日期 |
1995.11.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DEAN, MARK EDWARD;NGUYEN, THOI |
分类号 |
G06F15/16;G06F13/36;G06F13/38;G06F13/40;G06F15/177;(IPC1-7):G06F13/00 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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