Dynamic random access memory fabrication method having stacked capacitors with increased capacitance

摘要

A method for making an array of DRAM cells having increased capacitance was achieved. The method forms a planar insulating layer in which are etched capacitor node contact openings to each FET in an array of cells. A first polysilicon layer is deposited to fill the node contact openings and provide a polysilicon planar surface on the insulating layer. A multilayer of alternate layers of a traditional LPCVD silicon oxide and O3/TEOS silicon oxide is deposited and patterned having openings aligned over the capacitor node contacts where the capacitors are required. The multilayer is then etched in HF to partially etch and recess the faster etching O3/TEOS oxide, forming grooves in the sidewalls of the multilayer structure. A second polysilicon layer is then conformally deposited, etched back and the exposed multilayer structure is selectively removed in HF to leave free-standing bottom electrodes having sidewall spacers and a center pillar that replicate the grooves in the multilayer, thereby providing increased surface area. An interelectrode dielectric layer is formed on the bottom electrodes and a third polysilicon layer is deposited and patterned to form the top electrodes and to complete the array of stacked capacitors on the DRAM device.