| 摘要 |
A CMOS layout enables the matching of an intentionally created parasitic capacitance to an existing parasitic capacitance, for example, a gate-to-drain capacitance of a MOSFET, with a high degree of precision. This precise matching allows a differential pair of MOSFETs acting as the input of an amplfier to have intentionally created capacitances (that match the parasitic gate-to-drain capacitances) cross-coupled between the inputs and the outputs of the differential pair. This cross-coupling of matching capacitances effectively cancels the bandwidth reducing effect of the gate-to-drain capacitances of the differential pair. The layout provides for the interdigitation of the gates of the differential pair, with each input transistor comprising at least two transistors connected together to form a single input transistor. Each of these input transistors, in turn, has a gate placed near the drains of the at least two (connected) devices, thus forming intentionally created parasitic capacitances between the gate and each of the two drains. In this arrangement, the two created parasitic capacitance match the two gate-to-drain parasitic capacitances with a high degree of precision due to the proximity of the devices and the lack of interconnections between them. Also, by using mirrored symmetry in the layout, the effects of gradients in the materials forming the devices are averaged out for each device.
|
