发明名称 |
Semiconductor memory device |
摘要 |
A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.
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申请公布号 |
US5768210(A) |
申请公布日期 |
1998.06.16 |
申请号 |
US19970833045 |
申请日期 |
1997.04.03 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
MATSUI, KATSUAKI;ISHIMURA, TAMIHIRO |
分类号 |
G11C11/41;G11C7/10;G11C11/401;G11C11/409;G11C11/4096;G11C11/419;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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