发明名称 |
Method and apparatus for adjusting phase-lock-loop parameters |
摘要 |
A method and apparatus for adjusting the parameters of a PLL in a communication system. The method measures the rate of transmission of clock reference information by measuring the time of arrival of successive clock references or the difference of the clock reference values. The method applies the measured transmission rate to a plurality of predefined transmission rate ranges to acquire the proper gain factor values. These gain factor values are used to control the responsiveness of the PLL to new clock reference information.
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申请公布号 |
US5767746(A) |
申请公布日期 |
1998.06.16 |
申请号 |
US19960660300 |
申请日期 |
1996.06.07 |
申请人 |
DAVID SARNOFF RESEARCH CENTER, INC.;SHARP KK |
发明人 |
DIETERICH, CHARLES BENJAMIN |
分类号 |
H03L7/107;H03L7/093;H03L7/113;H03L7/181;H04L7/033;H04N7/62;(IPC1-7):H03L7/197 |
主分类号 |
H03L7/107 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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