发明名称 |
Multi processor system |
摘要 |
<p>A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.</p> |
申请公布号 |
EP0848318(A2) |
申请公布日期 |
1998.06.17 |
申请号 |
EP19970309790 |
申请日期 |
1997.12.04 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARROYO, RONALD XAVIER ARROYO;PHAM, KHUONG HUU PHAM |
分类号 |
G06F1/08;(IPC1-7):G06F1/12 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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