PLL circuit and digital signal reproducing apparatus

摘要

A PLL circuit which is used as a reproducing clock forming circuit of a digital signal reproducing apparatus. The PLL circuit is strong against noises and has stable characteristics. Comparison outputs of a phase comparator 3 are outputted in a form of balance (differential) signals and are supplied to a loop filer 4. Output signals of the loop filter 4 are supplied to control voltage input terminals of a VCO 5 in a form of the balance signals. In-phase components of the noises included in control voltages can be cancelled. Time constants of the loop filter can be switched by bipolar transistors Tr31 and Tr32. A balance of the balance signals is not broken by base currents of the transistors Tr31 and Tr32.