| 摘要 |
A data processing apparatus capable of receiving a CPU of different data bus widths is disclosed. Terminals for the lower 32 bits of a 64-bit data bus and terminals for upper 32 bits of the 64-bit data bus are provided opposing to one another at a connector. Also, terminals for the lower 3 bits of a byte enable signal and terminals for the upper 4 bits of the byte enable signal are disposed opposing one another. When a first CPU module having a 32-bit CPU is installed, a bus connector board is coupled to the connector to couple the corresponding terminals of the lower 32 bits and the upper 32 bits, and the corresponding terminals of the lower 3 bits and the upper 4 bits of the byte enable signal.
|
