发明名称 Interpolation system for fixed sample rate signal processing
摘要 Using digital signal processing in a modem attached to a digital line, the modem sample rate for both transmit and receive signals is interpolated or decimated to the time slot rate of a digital channel connected to the modem by filters which are operated by a unified interpolation/decimation filter controller as a function of a modulo counter. For example, a modem signal is developed as if it were to be supplied to a codec. However, instead of being supplied to the codec, the signal is filtered using a low pass finite impulse response digital filter. The resulting filtered signal is sampled at the time slot rate and supplied in companded form as an output to the time slots of the digital line. Prior to operating the filter, the ratio of the time slot rate to the sample rate is determined. The ratio is expressed in a form that is a ratio of the smallest possible integers. The numerator of the resulting ratio is designated P and the denominator is designated I. The coordination between the development of the modem signal sample and the filter operation is under the control of a modulo counter that has a modulus of P.
申请公布号 US5768311(A) 申请公布日期 1998.06.16
申请号 US19950577786 申请日期 1995.12.22
申请人 PARADYNE CORPORATION 发明人 BETTS, WILLIAM LEWIS;SOUDERS, KEITH ALAN
分类号 H03H17/06;H04L5/16;H04L25/05;(IPC1-7):H04B1/38 主分类号 H03H17/06
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