| 摘要 |
In a ferrolectric memory, semiconductor memory cells are arranged in a matrix array of rows and columns and connected respectively to plate lines, word lines and bit lines for changing polarization states of the capacitor of an addressed memory cell in response to operating voltages. First, second and third terminals are provided. A first set of conducting devices establishes branched paths from the first terminal to the plate lines when a first potential is applied to the first terminal, and a second set of conducting devices establishes branched paths from the second terminal to the word lines when a second potential is applied to the second terminal. A third set of conducting devices establishes branched paths from the third terminal to the bit lines when a third potential is applied to the third terminal. If the ferroelectric capacitor of at least one of the memory cells is short-circuited, a sufficient current will flow into the cell to heal the faulty condition.
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