| 摘要 |
A first test circuit (21) is connected to one end of a first wiring line (40), and a second test circuit (22) is connected to one end of a second wiring line (41). The second wiring line (41) serves as a data bus. N-channel MOS transistors (50, 51), connected in series, are provided between the first and second wiring lines (40, 41) and located below a third wiring line (42). The transistors (50, 51) are set in an conductive state by a gate control signal (TEST) from a test control circuit (53) in a test mode, and are set in an OFF state in a normal operation mode. In the normal operation mode, the capacitance between the first and second wiring lines (40, 41) is small and does not adversely affect the operation speed of an integrated circuit. <IMAGE> |
