Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen

摘要

The invention relates to a unit which is controlled by a logical load unit (PLU), and which can be configured or reconfigured during running time, according to the following configuration: the invention provides for a programmable arithmetic logic unit (EALU), whose function and network connection are programmed in registers in which a plurality of data can be processed without reprogramming of the processing elements (PAE). To control the arithmetic logic unit (EALU), the invention provides for a state machine (SM-UNIT); it further provides registers for each operand (O-REG) and the result (R-REG), which are designed in part to act as shift registers. Feedback of the data of the results register takes place via a multiplexer (R20-MUX) to one of the inputs of the EALU. A bus multiplexing unit (BM-UNIT) makes it possible for the data to be taken from a bus system or for the result to be fed into a bus system, whereby the bus unit can send data to several receivers and synchronisation, even of several receivers, takes place automatically. The registers prevent the data processing system in the EALU to have access to the bus, so that each PAE can be considered an independent unit in that the configuration or reconfiguration of a PAE does not disturb the data originators and receivers or the independent PAEs.