Apparatus for dividing a signal period into N quasi-equal shares

摘要

The subdivider receives an input signal with a period which is divided into N quasi-equal blocks. A clock (1) produces A pulses, equal to 2<P><+><M> or less, during one input period of what would normally be a TV vertical synchronisation signal (VSYNC). A first M-bit register (4) stores R pulses equal to the remainder of A/N where N = 2<M> while a second P-bit register (5) stores the quotient of the same calculation. An accumulator (7) produces ones and zeroes at a rate of R values equal to one over a group of N numbers and a summer (8) adds the output of the accumulator to the contents of the second register to give an input to a P-bit binary counter (3). The counter receives the clock input and produces an end of block signal (F) which initiates the accumulator.