Semiconductor memory with numerous pairs of bit lines

摘要

The memory has each cell containing a part of binary data. An operational mode adjuster (120) activates a first operational mode in response to an external data signal (SBT). An inner address generator (122,124,130) transmits an inner address signal cyclically in response to activation of the first operating mode signal. This address signal sequentially selects a memory cell for data writing. A data generator (174,176) transmits inner data to the cell selector to write inner binary data in a control pattern into the cells sequentially selected by inner address signals in dependence on the bit and word lines and the memory cells.