High speed active bus

摘要

A high speed bus structure which makes the bus effective and practical to use for both single processor and multiple processor environments. This is achieved by providing an active bus wherein a number of logic functions which control the operation of the bus are removed from the modules and are centralized and incorporated into the bus. The amount of bus functionality provided by the modules is minimized therefore decreasing the complexity and computational overhead of the modules and traffic on the bus that are attributable to supporting the functionality to operate the bus. The number of bussed signal lines is minimized by eliminating the bussed lines relevant to the centralized bus functions. In place of the bussed signal lines, dedicated signal lines connect the modules inserted into the bus and the bus components providing the centralized logic functions. Thus certain states or commands which were separate commands are now incorporated into one of the basic bus commands or communicated through dedicated signal lines which connect the centralized bus components and the modules. Furthermore, certain signal lines not considered to be directly related to system performance are eliminated and incorporated into a bus transaction.