发明名称 |
Methods for automatically pipelining loops |
摘要 |
A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.
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申请公布号 |
US5764951(A) |
申请公布日期 |
1998.06.09 |
申请号 |
US19950440554 |
申请日期 |
1995.05.12 |
申请人 |
SYNOPSYS, INC. |
发明人 |
LY, TAI A.;KNAPP, DAVID W.;MILLER, RONALD A.;MACMILLEN, DONALD B. |
分类号 |
G06F17/50;(IPC1-7):G06F9/455 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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