发明名称 |
Semiconductor memory device and method of checking same for defect |
摘要 |
A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
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申请公布号 |
US5764576(A) |
申请公布日期 |
1998.06.09 |
申请号 |
US19960752419 |
申请日期 |
1996.11.19 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
HIDAKA, HIDETO;ASAKURA, MIKIO;FURUTANI, KIYOHIRO;KATO, TETSUO |
分类号 |
G11C11/413;G11C11/401;G11C29/00;G11C29/04;G11C29/14;G11C29/24;(IPC1-7):G11C29/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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