| 摘要 |
<p>PROBLEM TO BE SOLVED: To smoothly switch between asynchronous clocks during a processor operation in a clock acquisition subsystem for an electronic data processing system. SOLUTION: An interlocked clock multiplexer 100 which acquires a clock source that is supplied as a clock signal 102 to a data processing system connects at least two input terminals 104 and 106 to more than two clock sources 110 and 120. When switching between them is carried out, an interlocked synchronizer that is included in the multiplexer 100 is used, also a selection signal 108 from a control register 130 is responded to, and an output clock signal 102 is transferred from a 1st clock source to a 2nd clock source cleanly like 'no glitch'.</p> |
