| 摘要 |
An improved decoder apparatus and method for memory-array read operations are presented. The improved decoder apparatus includes a number of row decoder circuits such that each row decoder circuit includes a footed domino circuit having a pull-down device located within a pull-down path of the footed domino circuit. The improved decoder apparatus further includes a common shared node coupled to each pull-down device such that the shared common node allows the pull-down strength of each pull-down device to be increased proportionally to the number of row decoder circuits which share the common shared node, thereby promoting increased decoding operational rates and faster memory-array read operations. The pull-down device can be an N-type pull-down device. In addition, each row decoder circuit includes an address predecoder, coupled to the footed domino circuit, that receives a number of address inputs and combines address inputs into a single digital signal for utilization by the improved decoder apparatus. In addition each row decoder circuit includes a wordline driver circuit, coupled to the footed domino circuit, for providing an output of the decoder apparatus to a wordline. The improved decoder apparatus decodes address data submitted in 2B encoded format.
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