Pipelined clock distribution for self resetting CMOS circuits

摘要

A system for clocking self resetting CMOS (SRCMOS) circuits operating at high speed includes a clock generator circuit which produces a first pipeline clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first pipeline clock, a number of delay circuits, the time duration of each of the delay circuits being determined by characteristics of evaluation logic in the SRCMOS circuits being clocked, the delay circuits being connected in a serial pipeline fashion such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration. The clocking system also includes a cycle relax mode whereby the clock pulse output of the clock generator circuit may be extended for test or diagnostic purposes.